1. Field of the Invention
The present invention relates to a delay controlling circuit for delaying an input signal for a predetermined amount of time and a phase compensating apparatus for compensating the difference in phases of signals.
2. Description of the Related Art
As the processing speed of computer systems increases, the difference in phases of the internal clock and the system clock due to delays in clock distributing circuits in LSI devices becomes large. Thus, a phase compensating circuit for synchronizing the phase of the internal clock with the phase of the system clock is required.
As a phase compensating circuit, a PLL (phase locked loop) circuit is used. FIG. 1 is a block diagram showing a structure of a conventional PLL circuit having a voltage controlled oscillator. FIG. 2 is a block diagram showing a structure of a conventional PLL circuit having a voltage controlled delaying circuit.
In FIG. 1, a phase/frequency comparator 1 compares the phase of the internal clock signal with the phase of the external clock signal. A signal corresponding to the phase difference is supplied to a charge pump/low pass filter 2. The charge pump/low pass filter 2 supplies an analog control signal corresponding to the compared result of the phase/frequency comparator 1 to a voltage controlled oscillator 3. In addition, the charge pump/low pass filter 2 removes high frequency noise.
A voltage controlled oscillator 3 generates a clock signal with a frequency corresponding to the analog control signal that is received from the charge pump/low pass filter 2. The clock signal generated by the voltage controlled oscillator 3 is supplied by a clock distributing circuit 4 to each circuit portion of the LSI device as the internal clock signal. The internal clock signal is fed back to the phase/frequency comparator 1.
Next, the operation of the above-described PLL circuit will be described. When the phase (or frequency) of the external clock signal does not accord with the phase (or frequency) of the internal clock signal, an analog control signal corresponding to the phase difference between the clock signals is supplied to the voltage controlled oscillator 3. Thus, the oscillating frequency is controlled so that the phase difference decreases. A clock signal with a new frequency generated by the voltage controlled oscillator 3 is fed back to the phase/frequency comparator 1. These operations are repeated continuously. Thus, the oscillating frequency is controlled so that the phase of the external clock signal accords with the phase of the internal clock signal.
FIG. 2 is a block diagram showing a structure of a conventional PLL circuit having a voltage controlled delaying circuit 5 instead of the voltage controlled oscillator 3. The difference between the circuit shown in FIG. 2 and the circuit shown in FIG. 1 is in that the voltage controlled delaying circuit 5 designates an amount of delay for the external clock signal corresponding to the analog control signal received from the charge pump/low pass filter 2, and delays the external clock signal for the amount of delay time so that the phase of the internal clock signal accords with the phase of the external clock signal.
In PLL controlling circuits, the ratio of the change of the phase of the output signal to the detected phase difference is the loop gain. To decrease the lock time by which the phase difference value comes within a predetermined range, it is necessary to increase the loop gain. On the other hand, to improve the stability of the output signal, it is necessary to decrease the loop gain.
In the conventional analog controlled PLL circuit, a decrease in the lock time is in contradiction to the stability of the system. When the stability of the system is improved, the lock time increases. In contrast, when the lock time is decreased, the system becomes unstable.
In addition, when the above-described PLL controlling circuit is disposed in an LSI device, it is accomplished as an analog circuit using a CMOS process or the like. However, the characteristics of the charge pump and low pass filter as factors for obtaining the loop gain remarkably depend on the fabrication conditions of the LSI device. Thus, the stability of the system and the responsive characteristic thereof significantly vary corresponding to the fabrication conditions of the LSI device.